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參數(shù)資料
| 型號： | MT80C154-L16 |
| 英文描述： | CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| 中文描述： | 的CMOS 0至36 MHz的單芯片8位微控制器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 354K |
| 代理商： | MT80C154-L16 |
Rev.F (14 Jan. 97)
19
MATRA MHS
A : Address.
C : Clock.
D : Input data.
H : Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P : PSEN.
Q : Output data.
R : READ signal.
T : Time.
V : Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
AC Parameters
TA = 0 to + 70
°
C ; Vss = 0 V ; Vcc = 5 V
±
10 % ; F = 0 to 36 MHz
TA = –55
°
+ 125
°
C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz
TA = –55
°
+ 125
°
C ; Vss = 0 V ; Vcc = 5 V
±
10 % ; F = 0 to 36 MHz
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)
External Program Memory Characteristics
16 MHz
20 MHz
25 MHz
30 MHz
36 MHz
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TLHLL
ALE Pulse Width
110
90
70
60
50
TAVLL
Address valid to ALE
40
30
20
15
10
TLLAX
Address Hold After ALE
35
35
35
35
35
TLLIV
ALE to valid instr in
185
170
130
100
80
TLLPL
ALE to PSEN
45
40
30
25
20
TPLPH
PSEN pulse Width
165
130
100
80
75
TPLIV
PSEN to valid instr in
125
110
85
65
50
TPXIX
Input instr Hold After PSEN
0
0
0
0
0
TPXIZ
Input instr Float After PSEN
50
45
35
30
25
TPXAV
PSEN to Address Valid
55
50
40
35
30
TAVIV
Address to Valid instr in
230
210
170
130
90
TPLAZ
PSEN low to Address Float
10
10
8
6
5
External Program Memory Read Cycle
TAVIV
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