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參數(shù)資料
| 型號： | MT70003 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | SINGLE CHANNEL ARINC DECODER |
| 中文描述： | 單通道ARINC公司譯碼器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 143K |
| 代理商： | MT70003 |
MT70003
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
5
If either mode of operation is an address recognition signal is not detected within 4
μ
s of TAG VALID being
set this flag is automatically cancelled and the word latch is not updated. Conversely, if an address
recognition signal is detected within 4
μ
s of TAG VALID being set and is held for at least until 6
μ
s after the
rising edge of TAG VALID then the word latch is updated. TAG VALID then stays HI until cancelled either
by data access complete or the detection of the end of the next received word.
Data Bus
The contents of the word latch is output onto a data bus enabled by a LO on NOT DATA ENABLE. The
status of the output bus is indicated by DATA READY. This flag is automatically held LO whenever DATA
ENABLE ia HI. DATA READY is held LO for the duration of the internal sequence, whilst NOT RESET
DATA READY is held LO and whilst DATA MUX and the output date are settling. Otherwise DATA
READY is set soon after the word latch has been updated and cancelled when data access is complete.
24 Bit Option
For the 24 bit format 16/24 BUS SELECT is wired LO. DATA MUX is always HI to indicate that bits 17 to
32 are output on D1/17 and D16/32 respectively and in addition bits 9 to 16 are output on D9 to D16. Data
access is complete when the user pulses NOT RESET DATA READY with a single LO pulse of width greater
than 100 ns.
16 Bit Option
16/24 BUS SELECT is wired HI. DATA MUX is reset by the sequencer at the end of word. When DATA
READY is set, bits 1 to 16 are available on D1/17 to D1/32 respectively. The user signals acceptance of the
first half by pulsing NOT RESET DATA READY LO. Then DATA READY cancels whilst DATA MUX and
DATA READY has been taken HI, DATA READY re-appears. DATA MUX is now HI and bits 17 to 32
available on D1/17 to D16/32. Data access is complete when NOT RESET DATA READY is pulsed LO for
a second time.
End of Word Detection
This is detected by a gap counter which times out whilst ‘O’ DETECT and ‘1’ DETECT are LO for a time
equivalent to 2
2
bit periods. Having timed out it generates an end of word signal which sets OVERRUN if
TAG VALID is still HI and triggers the control sequencer.
Bit Counter
This counts the number of shift pulses applied to the shift register. It is not allowed to count past state 33 and
is reset by the control sequencer. For a good word to be detected it must be in state 32 at the end of the word.
Parity Checker
This is reset along with the bit counter. It toggles whenever a logic ‘1’ is shifted into the register. For a good
word to be detected it must be in a HI state at the end of the word.
Circuit Initialisation
The circuit can be initialised at any time by holding NOT RESET LO. This pin has an internal pull-up
transistor. All the flags are immediately cleared and the circuit is locked whilst NOT RESET is LO. The
minimum duration of LO is 200 ns. The removal of the reset condition occurs on a rising edge of
IN
following NOT RESET going HI.
APPLICATIONS
Instrument Displays
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