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參數(shù)資料
| 型號(hào)： | MT58L64V36P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 64K的× 36，流水線，SCD的SyncBurst的SRAM（處理器，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 487K |
| 代理商： | MT58L64V36P |
21
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE:
1. D(A2) refers to input for address A2. Q(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device;
or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
-5
-6
-7.5
-10
SYMBOL
t
DS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
DH
t
CEH
MIN MAX MIN MAX MIN MAX MIN MAX
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2.2
2.2
0.5
0.5
0.5
0.5
0.5
0.5
WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
OEHZ
t
AS
t
ADSS
t
AAS
t
WS
MIN MAX MIN MAX MIN MAX MIN MAX
5.0
6.0
200
166
1.6
1.7
1.6
1.7
3.0
3.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
7.5
10
133
100
1.9
1.9
3.2
3.2
4.0
4.5
1.5
1.5
1.5
1.5
2.2
2.2
2.2
2.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L128L32D1 | 128K x 32，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L36D1 | 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L32P1 | 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128L36P1 | 128K x 36，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L128V32P1 | 128K x 32， Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64V36PT-5 | 制造商:Micron Technology Inc 功能描述: |
| MT58L64V36PT-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT58LC128K18B4LG-8.5 | 制造商:Cypress Semiconductor 功能描述:128KX18 SRAM PLASTIC TQFP 3.3V |
| MT58LC128K18C6LG-7.5 | 制造商:Cypress Semiconductor 功能描述:EOL, REPLACE WITH MT58L128L18D |
| MT58LC128K18D9LG-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
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