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參數(shù)資料
| 型號： | MT54W4MH9B-6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MT54W4MH9B-6 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
19
2002, Micron Technology Inc.
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
The QDR SRAM incorporates a serial boundary scan
test access port (TAP). This port operates in accor-
dance with IEEE Standard 1149.1-2001. The TAP oper-
ates using JEDEC-standard 1.8V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V
SS
) to prevent clocking of the device.
TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
V
DD
through a pull-up resistor. TDO should be left
unconnected. Upon power-up, the device will come up
in a reset state, which will not interfere with the opera-
tion of the device
.
TEST ACCESS PORT (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Figure 7
TAP Controller State Diagram
NOTE:
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
Test Data-In (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most-signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-
out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 7.) The output changes on the falling edge of
TCK. TDO is connected to the least-significant bit
(LSB) of any register, as depicted in Figure 8.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT54W4MH9B-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-4 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-6 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54W4MH9B-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
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