參數(shù)資料
型號: MT4LDT464HX
廠商: Micron Technology, Inc.
英文描述: SMALL-OUTLINE DRAM MODULE
中文描述: 小外形DRAM模塊
文件頁數(shù): 16/32頁
文件大小: 625K
代理商: MT4LDT464HX
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
16
4, 8 MEG x 64
DRAM SODIMMs
NOTES (continued)
2
8.LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
t
OEH is met. If CAS# goes HIGH prior
to OE# going back LOW, the DQs will remain
open.
29.The SPD EEPROM WRITE cycle time (
t
WR) is the
time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
30.V
IH
overshoot: V
IH
(MAX) = V
DD
+ 2V for a pulse
width
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
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