參數(shù)資料
型號： MT48LC8M16A2FB-7E
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 37/59頁
文件大?。?/td> 1822K
代理商： MT48LC8M16A2FB-7E
37
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
INITIALIZE AND LOAD MODE REGISTER
1
*CAS latency indicated in parentheses.
NOTE:
1. If CS# is HIGH at clock HIGH time, all commands applied are NOP, with CKE a
“
Don
’
t Care.
”
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
-7E
-75
-8E
SYMBOL*
t
CKS
t
CMH
t
CMS
t
MRD
3
t
RFC
t
RP
MIN
1.5
0.8
1.5
2
66
15
MAX
MIN
1.5
0.8
1.5
2
66
20
MAX
MIN
2
1
2
2
70
20
MAX
UNITS
ns
ns
ns
t
CK
ns
ns
TIMING PARAMETERS
-7E
-75
-8E
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
MAX
MIN
1
2
3
3
8
10
1
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
tCH
tCL
tCK
CKE
CLK
COMMAND
DQ
BA0, BA1
BANK
tRFC
tMRD
tRFC
AUTO REFRESH
AUTO REFRESH
Program Mode Register
2, 3, 4
tCMH
tCMS
Precharge
all banks
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tRP
(
)
(
)
(
)
(
)
tCKS
Power-up:
V
DD
and
CLK stable
T = 100μs
MIN
PRECHARGE
NOP
RAUTO
NOP
LREGISTER
ACTIVE
NOP
NOP
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
RAUTO
ALL
BANKS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
High-Z
tCKH
(
)
(
)
(
)
(
)
DQM /
DQML, DQMH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
()()
()()
()()
()()
()()
NOP
(
)
(
)
(
)
(
)
tCMH
tCMS
tCMH
tCMS
A0-A9, A11
ROW
tAH
tAS
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
A10
ROW
tAH
tAS
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
ALL BANKS
SINGLE BANK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON
’
T CARE
T0
T1
Tn + 1
To + 1
Tp + 1
Tp + 2
Tp + 3
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