參數(shù)資料
型號: MT48H8M16LFB4-8IT:JTR
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù): 3/61頁
文件大小: 2469K
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
11
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Mode Register Definition
Preliminary
Figure 4:
Mode Register Definition
Notes:
1. The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 4, “Burst Definition1,” on page 10.
10
M3 = 0
1
2
4
8
Reserved
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS LatencyBT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
54
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
Reserved*WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
BA0
BA1
M9
M7 M6
M5
M4
M3
M8
M2
M1
M0
M10
11
A11
M11
M12
M13
Register Select
13
Base Mode Register
Extended Mode Register
1
0
M13
M12
0
Reserved
12
Reserved
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