參數(shù)資料
型號(hào)： MT46V64M8TG-75Z
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 47/68頁(yè)
文件大?。?/td> 2555K
代理商： MT46V64M8TG-75Z
47
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
CAPACITANCE (x16)
(Note: 13; notes appear on pages 50
–
53)
PARAMETER
Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IOL
DC
IOU
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
–
–
–
–
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
NOTES
24
24
29
29
I
DD
SPECIFICATIONS AND CONDITIONS (x16)
(Notes: 1
–
5, 10, 12, 14; notes appear on pages 50
–
53) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC
(MIN)
;
t
CK =
t
CK
(MIN)
; DQ, DM, and DQS inputs changing once per clock cyle;
Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
RC =
t
RC(MIN);
t
CK =
t
CK(MIN); I
OUT
= 0mA; Address and control inputs
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK(MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;
t
CK =
t
CK
(MIN)
;
CKE = HIGH; Address and other control inputs changing once per clock cycle.
V
IN
=
V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK(MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
t
RC =
t
RAS(MAX);
t
CK =
t
CK(MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK(MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SYMBOL
-75/-75Z
I
DD
0
-8
UNITS NOTES
mA
TBD
TBD
22, 48
I
DD
1
TBD
TBD
mA
22, 48
I
DD
2P
3
3
mA
23, 32
50
51
I
DD
2F
40
35
mA
I
DD
3P
3
3
mA
23, 32
50
22
I
DD
3N
35
30
mA
I
DD
4R
TBD
TBD
mA
22, 48
I
DD
4W
TBD
TBD
mA
22
t
RC =
7.8125μs
t
RC =
7.8125μs
Standard
Low power (L)
I
DD
5
I
DD
5
I
DD
6
I
DD
7
I
DD
7
6
6
6
6
mA
mA
mA
mA
mA
27,50
27,50
11
11
22, 49
SELF REFRESH CURRENT: CKE
≤
0.2V
TBD
TBD
TBD
TBD
TBD
TBD
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge with ,
t
RC =
t
RC
(MIN)
;
t
CK =
t
RC
(MIN)
; Address and
control inputs change only during Active READ, or WRITE commands.
MAX
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