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512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
BANK WRITE
–
WITH AUTO PRECHARGE
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
tCL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
IH
RA
t
RCD
t
RAS
t
RP
t
WR
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T4n
NOTE:
1. DI
n
= data-out from column
n
; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6
. tDSH is applicable during tDQSS
(
MIN)
and is referenced from CK T4 or T5.
7
.tDSS is applicable during tDQSS
(MAX)
and is referenced from CK T5 or T6.
NOP5
NOP5
COMMAND
4
3
ACT
RA
RA
Col
n
WRITE2
NOP5
Bank
x
NOP5
Bank
x
NOP5
NOP5
NOP5
t
DQSL
t
DQSH
t
WPST
DQ
1
DQS
DM
DI
b
t
DS
t
DH
t
DQSS
(NOM)
DON
’
T CARE
TRANSITIONING DATA
t
WPRES
t
WPRE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
-75Z
-75
-8
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
t
DSS
MIN
0.45
0.45
7.5
7.5
0.5
0.5
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
MIN
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
MIN
0.45
0.45
8
10
0.6
0.6
0.35
0.35
0.75
0.2
MAX
0.55
0.55
13
13
UNITS
t
CK
t
CK
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
1.25
1.25
1.25
-75Z
-75
-8
SYMBOL
t
DSH
t
IH
t
IS
t
RAS
t
RCD
t
RP
t
WPRE
t
WPRES
t
WPST
t
WR
MIN
0.2
1
1
40
20
20
0.25
0
0.4
15
MAX
MIN
0.2
1
1
40
20
20
0.25
0
0.4
15
MAX
MIN
0.2
1.1
1.1
40
20
20
0.25
0
0.4
15
MAX
UNITS
t
CK
ns
ns
ns
ns
ns
t
CK
ns
t
CK
ns
120,000
120,000
120,000
0.6
0.6
0.6
TIMING PARAMETERS