參數(shù)資料
型號： MT46H256M32L4MC-54AT:A
元件分類： DRAM
英文描述： 256M X 32 DDR DRAM, 5 ns, PBGA240
封裝： 14 X 14 MM, GREEN, PLASTIC, WFBGA-240
文件頁數(shù)： 81/106頁
文件大?。?/td> 3431K
Figure 37: READ-to-PRECHARGE
CK
CK#
T0
T1
T2
T3
T2n
T3n
T4
T5
T1n
CK
CK#
T0
T1
T2
T3
T2n
T3n
T4
T5
T1n
Command
READ1
NOP
PRE2
NOP
ACT3
Address
Banka,
Col n
Bank a,
(a or all)
Bank a,
Row
Banka,
Col n
Bank a,
(a or all)
Bank a,
Row
DQ4
DQS
CL = 2
tRP
READ1
NOP
PRE2
NOP
ACT3
Command
Address
DQ4
DQS
CL = 3
tRP
Don’t Care
Transitioning Data
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
Notes: 1. BL = 4, or an interrupted burst of 8 or 16.
2. PRE = PRECHARGE command.
3. ACT = ACTIVE command.
4. DOUTn = data-out from column n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
7. A READ command with auto precharge enabled, provided tRAS (MIN) is met, would
cause a precharge to be performed at x number of clock cycles after the READ com-
mand, where x = BL/2.
2Gb: x16, x32 Mobile LPDDR SDRAM
READ Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
76
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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