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參數(shù)資料
| 型號： | MT34013 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | EIGHT CHANNEL ARINC DECODER |
| 中文描述： | ARINC公司的八通道解碼器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MT34013 |
MT34013
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
7
FIG. 3 MULTICHANNEL ARINC 429 RECEIVER OUTPUT TIMING
T
Clock Period (500 - 800nS).
Min
Max
t
ON
NOT CHIP ENABLE low to output active time.
10nS
250nS
tv
NOT OUTPUT SELECT low to word valid time.
300nS
t
SH (MIN)
minimum NOT OUTPUT SELECT high time.
400nS
t
SL (MIN)
minimum NOT OUTPUT SELECT low time.
400nS
tc
NOT CHIP ENABLE high to DATA READY low time.
100nS
2T + 500nS
t
OFF
NOT CHIP ENABLE high to data bus high impedance time. 20nS
100nS
t
CE (MIN)
minimum time NOT CHIP ENABLE high/low.
2.5T
t
CEDRH
minimum time to select next word (CHIP ENABLE high
to DATA READY high).
4T + 20nS
6T + 300nS
Notes:-
(1)
The CHIP ENABLE line going high during the select timing resets DATA READY and terminates the read
action. Not all 3 words (or 5 bytes) need to be accessed and read termination can take place at any time.
(2)
The output timing for the 8 bit parallel bus is similar to the above but with 5 byte accesses required.
(3)
The NOT CHIP ENABLE line cannot be held permanently low (see (1)).
(4)
All timings are theoretical and are based on a load of 100pF and one standard TTL input.
(5)
The NOT OUTPUT SELECT line only affects the chip when NOT CHIP ENABLE is low.
(6)
In BYTE mode, NOT CHIP ENABLE low to NOT OUTPUT SELECT low, (tsu) must be > 100nS to ensure
correct BYTE output sequence.
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