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參數(shù)資料
| 型號： | MT16LSDT6464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM MODULE |
| 中文描述： | 同步DRAM模塊 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 614K |
| 代理商： | MT16LSDT6464A |
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
21
2002, Micron Technology Inc.
Table 22: Serial Presence-Detect Matrix
V
DD
= +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
DESCRIPTION
ENTRY
(VERSION)
MT8LSDT3264A(I)
MT16LSDT6464A(I)
0
1
2
3
4
5
6
7
8
9
NUMBER OF BYTES USED BY MICRON
TOTAL NUMBER OF SPD MEMORY BYTES
MEMORY TYPE
NUMBER OF ROWADDRESSES
NUMBER OF COLUMN ADDRESSES
NUMBER OF MODULE BANKS
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS
SDRAM CYCLE TIME,
t
CK
(CAS LATENCY = 3)
128
256
80
08
04
0D
0A
01
40
00
01
70
75
80
54
60
80
08
04
0D
0A
02
40
00
01
70
75
80
54
60
SDRAM
13
10
1 or 2
64
0
LVTTL
7ns (-13E)
7.5ns (-133)
8ns (-10E)
5.4ns (-13E/-133)
6ns (-10E)
10
SDRAM ACCESS FROM CLK,
t
AC
(CAS LATENCY = 3)
MODULE CONFIGURATION TYPE
REFRESH RATE/TYPE
SDRAM WIDTH (PRIMARY SDRAM)
ERROR-CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY FROM BACK-TO-BACK
RANDOM COLUMN ADDRESSES,
t
CCD
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ONS DRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES:GENERAL
SDRAM CYCLE TIME ,
t
CK
(CAS LATENCY = 2) 10 (-133/-10E) A0
SDRAMACCESSFROMCLK,
t
AC
(CAS LATENCY = 2)
SDRAM CYCLE TIME,
t
CK
(CAS LATENCY = 1)
SDRAM ACCESS FROM CLK,
t
AC
(CAS LATENCY = 1)
MINIMUM ROW PRECHARGE TIME,
t
RP
11
12
13
14
15
NONPARITY
7.8125μs/SELF
8
NONE
1
00
82
08
00
01
00
82
08
00
01
16
17
18
19
20
21
22
23
1, 2, 4, 8, PAGE
4
2, 3
0
0
UNBUFFERED
0E
7.5ns (13E)
10ns (-133/-10E)
8F
04
06
01
01
00
0E
75
A0
8F
04
06
01
01
00
0E
75
A0
24
5.4ns (-13E)
6ns (-133/-10E)
54
60
54
60
25
00
00
26
00
00
27
15ns (-13E)
20ns (-133/-10E)
14ns (-13E)
15ns (-133)
20ns (-10E)
15ns (-13E)
20ns (-133/-10E)
45ns (-13E)
44ns (133)
50ns (-10E)
0F
14
0E
0F
14
0F
14
2D
2C
32
0F
14
0E
0F
14
0F
14
2D
2C
32
28
MINIMUM ROW ACTIVE TO ROW ACTIVE,
t
RRD
29
MINIMUM RAS# TO CAS# DELAY,
t
RCD
30
MINIMUM RAS# PULSE WIDTH,
t
RAS (See note 1)
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