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參數資料
| 型號： | MSM82C54-2RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數據恢復及定時提取 |
| 英文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-24 |
| 文件頁數： | 21/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MSM82C54-2RS |
5/23
Semiconductor
MSM82C54-2RS/GS/JS
AC CHARACTERISTICS
Min.
Max.
Address Set-up Times to Falling Edge of RD
tAR
30
—ns
Chip Select Input Set-up Time to Falling Edge of RD
tSR
0
—ns
Parameter
Unit
Symbol
Conditions
Address Hold Time from Rising Edge of RD
tRA
0
—ns
RD Pulse Width
tRR
95
—ns
Data Access Time after Address Determination
tAD
—
184
ns
Delay Time from Rising Edge of RD to Data Floting State
tDF
5
65
ns
RD Recovery Time
tRV
165
—ns
Address Set-up Time to Falling Edge of WR
tAW
0
—ns
Chip Select Input Set-up Time to Falling Edge of WR
tSW
0
—ns
Address Hold Time from Rising Edge of WR
tWA
0
—ns
WR Pulse Width
tWW
95
—ns
Data Determination Set-up Time to Rising Edge of WR
tDW
85
—ns
Data Hold Time after Rising Edge of WR
tWD
0
—ns
WR Recovery Time
tRV
165
—ns
CLK Cycle Time
tCLK
100
D.C.
ns
CLK "H" Level Width
tPWH
30
—ns
CLK "L" Level Width
tPWL
50
—ns
CLK Rise Time
tr
—
25
ns
CLK Fall Time
tf
—
25
ns
GATE "H" Level Width
tGW
50
—ns
GATE "L" Level Width
tGL
50
—ns
GATE Input Set-up Time before Rising Edge of CLK
tGS
40
—ns
GATE Input Hold Time before Rising Edge of CLK
tGH
50
—ns
Output Delay Time after Falling Edge of CLK
tOD
—
100
ns
Output Delay Time after Falling Edge of GATE
tODG
—
100
ns
CLK Rise Delay Time after Rising Edge of WR for Count Value
Loading
tWC
0
55
ns
tWG
–5
40
ns
GATE sampling delay time after rising edge of WR for count
loading
tWO
—
240
ns
Output Delay Time after Falling Edge of WR for Mode Set
tCL
–40
40
ns
CLK Fall Set-up Time to Falling Edge of WR for Counter Latch
Command
CL = 150 pF
(VCC = 4.5 V to 5.5 V, Ta = –40°C to +85°C)
82C54-2
Data Access Time from Falling Edge of RD
tRD
—94
Read
Timing
Write
Timing
Clock
Gate
Timing
ns
Note:
Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
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