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參數(shù)資料
| 型號： | MSM82C54-2GS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| 封裝： | PLASTIC, SSOP-32 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MSM82C54-2GS-K |
7/23
Semiconductor
MSM82C54-2RS/GS/JS
DESCRIPTION OF PIN FUNCTIONS
16 bits
Adress Bus
Control Bus
D7 - 0
A1 A0
CS
8 bits
RD
WR
8 bits
Data Bus
MSM82C54-2
OUT GATE CLK
Counter #0
OUT GATE CLK
Counter #1
OUT GATE CLK
Counter #2
SYSTEM INTERFACING
D7 - D0
Name
Bidirectional
Data Bus
Input/Output
Pin Symbol
Input/Output
Function
RD
Read Input
Input
WR
Write Input
Input
A0, A1
Address Input
Input
CLK0 - 2
Clock Input
Input
GATE0 - 2
Gate Input
Input
Three-state 8-bit bidirectional data bus used when writing control
words and count value, and reading count values upon reception of
WR and RD signals from CPU.
CS
Chip Select
Input
Data transfer with the CPU is enabled when this pin is at low level.
When at high level, the data bus (D0 thru D7) is switched to high
impedance state where neither writing nor reading can be executed.
Internal registers, however, remain unchanged.
Data can be transferred from MSM82C54-2 to CPU when this pin is
at low level.
Data can be transferred from CPU to MSM82C54-2 when this pin is
at low level.
One of the three internal counters or the control word register is
selected by A0/A1 combination. These two pins are normally
connected to the two lower order bits of the address bus.
Supply of three clock signals to the three counters incorporated in
MSM82C54-2.
Control of starting, interruption, and restarting of counting in the
three respective counters in accordance with the set control word
contents.
OUT0 - 2
Counter Output
Output
Output of counter output wave form in accordance with the set
mode and count value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C54-2RS | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| MSM82C54-2GS | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| MSM9005-01GS-BK | 8 X 65 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP100 |
| MSM9005-XXGS-BK | 8 X 65 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C54-2J3 | 制造商:OKI Semiconductor 功能描述:CPU I/OS EOL311208 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2R3 | 制造商:OKI Semiconductor 功能描述:PROG'ABLE PERIPHERAL INTERFACE EOL211209 |
| MSM82C54-2RS | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:CMOS programmable timer 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER |
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