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參數(shù)資料
| 型號： | MSM82C37B-5GS-2K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 19/35頁 |
| 文件大小： | 330K |
| 代理商： | MSM82C37B-5GS-2K |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Status Register
This register is a read-only register used in CPU reading of the MSM82C37B-5 status. The four
higher order bits indicate the DMA transfer request status for each channel, ‘1’ being set when
the DREQ input signal is active.
The four lower order bits indicate whether the corresponding channel has reached the TC or not,
‘1’ being set when the TC status is reached. These four lower order bits are reset by status
register reading, or RESET input and master clearing. A description of each bit is outlined in
Figure 7
DB7
0: Channel 0 Has Not Reached TC
1: Channel 0 Has Reached TC
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0: Channel 1 Has Not Reached TC
1: Channel 1 Has Reached TC
0: Channel 2 Has Not Reached TC
1: Channel 2 Has Reached TC
0: Channel 3 Has Not Reached TC
1: Channel 3 Has Reached TC
0: Channel 0 Is Not Requesting
1: Channel 0 Is Requesting
0: Channel 1 Is Not Requesting
1: Channel 1 Is Requesting
0: Channel 2 Is Not Requesting
1: Channel 2 Is Requesting
0: Channel 3 Is Not Requesting
1: Channel 3 Is Requesting
Figure 7 Status Register
Temporary Register
The temporary register is a register where transfer data is held temporarily during memory-
memory transfers. Since the last item of data to be transferred is held after completion of the
transfer, this item can be read by the CPU.
Software Command
The MSM82C37B-5 is equipped with software commands for executing special operations to
ensure proper programming. Software command is irrespective of data bus contents.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C43GS-K | 20 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| MSM82C51A-2GS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| MSM82C54-2RS | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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