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參數(shù)資料
| 型號(hào)： | MSM8129W-35 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 35 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | MSM8129W-35 |
128K x 8 SRAM
MSM8129 - 020/025/35
Issue 2.0 : April 2001
Pin Definition
(WX & JX Pinout Page 4)
Description
The MSM8129 is a 1Mbit monolithic SRAM organised
as 128K x 8 with access times from 20ns to 35ns
available. The device is available in two 32 pin ceramic
surface mount packages. The device is directly TTL
compatible.
All versions can be screened in accordance with MIL-
STD-883C.
Block Diagram
Pin Functions
A0~A16
Address Inputs
D0~7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power (+5V)
GND
Ground
128K x 8 CMOS Fast Static RAM
Features
Fast Access Times of 020/025/35 ns
High Density Packages.
Single and Dual CS pinout variants
Operating Power
940 mW (max)
Standby Power
165 mW (max)
Completely Static Operation
May be processed in accordance with
MIL-STD-883C
Package Details
Pin Count
Descripion
Package Type
32
JLCC Package
J
32
LCC Package
W
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
X
AD
DR
E
S
B
U
F
E
R
RO
W
DEC
O
DE
R
D0
D7
WE
OE
CS
COLUMN I/O
COLUMN DECODER
Y ADDRESS BUFFER
I/O
BUFFER
512 x 2048
BIT
MEMORY
ARRAY
A7
A6
A5
A4
A3
A2
A1
A0
A12
A8
A14
A11
A9
A10
A13
A15
A16
J / W
D1
D2
D4
GN
D
D3
D5
D6
A1
2
A1
4
VC
C
A1
6
NC
A1
5
CS
2
14
15
18
16
17
19
20
4
3
32
2
1
31
30
D0
A0
A3
A1
A2
A4
A5
A6
A7
D7
CS1
A11
A10
OE
A9
A8
A13
WE
21
22
25
23
24
26
27
28
29
13
12
9
11
10
8
7
6
5
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