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products and documentation, please visit
freescale.com/DSP.
Features and Benefits
SixStarCoreDSPSC3850coresubsystems
operating at up to 1 GHz/8000 MMACS per
core and up to 48000 MMACS per device
Multi-acceleratorplatformenginefor
baseband (MAPLE-B)
Highly flexible, programmable Turbo and
Viterbi decoder supports configurable
decoding parameters. It can perform up
to 200 Mbps of Turbo decoding
(six iterations) or up to 115 Mbps of
K = 9 (zero tail) Viterbi decoding
FFT/iFFT for sizes 128, 256, 512, 1024 or
2048 points at up to 350 million samples
per second
DFT/iDFT for sizes up to 1536 points at
up to 175 million samples per second
Twomasterbusesfordatatransfers
from/to the system memory at total
throughput up to 50 Gbps
High-speed,high-bandwidthCLASSfabric
arbitrates between the DSP cores and
other CLASS masters to M2 memory, M3
memory, DDR controllers, MAPLE-B and
the configuration registers
TwoDDRcontrollerswithupto400MHz
clock (800 MHz data) rate and 32/64-
bit DDR2/3 SDRAM data bus. Supports
SODIMMs and up to 0.5 GB per controller
32-channelDMAcontroller
DualRISCcoreQUICCEnginesubsystem
operating at up to 500 MHz provides
parallel packet processing independent of
the DSP cores
Supports:
Two Gigabit Ethernet controllers
supporting RGMII or SGMII
Serial peripheral interface
HSSIthatsupportstwo4xSerDesports,
including:
Two Serial RapidIO controllers supporting
1x/4x operation up to 3.125 Gbaud
One PCI Express controller that supports
1x/2x/4x operation
Multiplexing capability for RapidIO,
PCI Express and SGMII signals through
the two SerDes ports
FourTDMinterfaces
UARTandI2C interfaces
Eightsoftwarewatchdogtimers
1616-bittimers
Two32-bitgeneralpurposetimerspercore
for RTOS support
I/Ointerruptconcentratorandvirtual
interrupt support
Eighthardwaresemaphores
32GPIOportsmultiplexedwithinterface
signals and IRQ inputs
OptionalSEC(MSC8156E)optimizedto
process all the encryption/decryption
algorithms associated with IPsec, IKE,
WTLS/WAP, SSL/TLS, AES, DES,
RC-4, SNOW-3G and Kasumi for
3G-LTE and 3GPP
Bootoptions:Ethernet,SerialRapidIO,I2C
and SPI
ThreeinputclocksandfivePLLs
JTAGTestAccessPort(TAP)andboundary
scan architecture designed to comply with
IEEE 1149.1 standard for profiling and
performance monitoring support
Reducedpowerdissipationwithwait,
stop and power down low-power
standby modes
Optimizedpowermanagementcircuitry
Technology:CMOS45nmSOItechnology
in 29 mm, 29 mm, 783 ball, FC-PBGA
package
Development Support
Freescale supplies a complete set of
CodeWarrior DSP development tools for
the MSC8156/MSC8156E device. The
tools provide easier and more robust ways
for designers to develop optimized DSP
systems. Whether the application targets a
3G-LTE, TD-SCDMA or WiMAX system, the
development environment gives designers
everything they need to exploit the advanced
capabilities of the MSC8156/MSC8156E
architecture.
Support tools include:
Eclipse-basedintegrateddevelopment
environment (IDE)
CandC++compilerwithin-lineassembly
Librarian
Multicoredebugger
Royalty-freeRTOS
Softwaresimulator
Profiler
High-speedruncontrol
Hostplatformsupport
MSC8156ADSdevelopmentboard
MSC8156EVMevaluationmodule
Contact your local sales office or
representative for availability.
Freescale, the Freescale logo, StarCore, QUICC Engine and CodeWarrior technologies are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. QUICC Engine is the trademark of Freescale Semiconductor, Inc. All other product or service names are the
property of their respective owners. 2010 Freescale Semiconductor, Inc.
Document Number: MSC8156FS
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