參數(shù)資料
型號(hào)： MR80C52TXXX-36SHXXX
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 11/60頁(yè)
文件大?。?/td> 5137K
代理商： MR80C52TXXX-36SHXXX
19
8266D-MCU Wireless-06/12
ATmega128RFA1
The five different addressing modes for the data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
In the Register file, registers R26 to R31 feature the indirect addressing pointer
registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM
in the ATmega128RFA1 are all accessible through all these addressing modes. The
Register File is described in "General Purpose Register File" on page 12.
Figure 8-7. Data Memory Map
32 Registers
64 I/O Registers
Internal SRAM
(16K x 8)
$0000 - $001F
$0020 - $005F
$41FF
$FFFF
$0060 - $01FF
Data Memory
416 Ext I/O Reg.
$0200
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
Access to the internal data SRAM is performed in two clkCPU cycles as described in
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