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參數(shù)資料
| 型號： | MR16R162GEG0-CK8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Key Timing Parameters |
| 中文描述： | 關(guān)鍵的定時參數(shù) |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 442K |
| 代理商： | MR16R162GEG0-CK8 |
Page 8
MR16R1624(8/G)EG0
MR18R1624(8/G)EG0
AC Electrical Specifications
Version 1.0 May 2004
Adjusted
T
PD
Specification
Table 8: AC Electrical Specifications
Symbol
Parameter and Conditions
Min
Typ
Max
Unit
Z
L
Module Impedance of RSL Signals
25.2
28
30.8
Z
UL-CMOS
Module Impedance of SCK and CMOS signals
23.8
28
32.2
T
PD
Propagation Delay variation of RSL signals. Average clock
delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN)
-
See
Table10
a,b
ns
T
PD
Propagation delay variation of RSL signals with respect to T
PD
b,c
for 4 and 8 device modules
-21
21
ps
Propagation delay variation of RSL signals with respect to T
PD
b,c
for 16 device modules
-24
24
ps
T
PD-CMOS
Propagation delay variation of SCK signals with respect to an
average clock delay
-250
250
ps
T
PD-SCK,CMD
Propagation delay variation of CMD signals with respect to SCK
signal
-200
200
ps
V
α
/V
IN
Attenuation Limit
See
Table10
a
%
V
XF
/V
IN
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
See
Table10
a
%
V
XB
/V
IN
Backward crosstalk coefficient (300ps input rise time @ 20%-
80%)
See
Table10
a
%
a. Table 10 lists parameters and specifications for different storage capacity RIMM Modules that use 256Mb or 288Mb RDRAM devices.
b. T
PD
or Average clock delay is defined as the delay from finger to finger of RSL signal.
c. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifica
tions, then the specification can be adjusted by the
“
Adjusted
T
PD
Specification
“
table 9 below.
Table 9: Adjusted
T
PD
Specification
Symbol
Parameter and Conditions
Adjusted Min/Max
Absolute
Min / Max
Unit
T
PD
Propagation delay variation of RSL signals with respect to
T
PD
for 4 and 8 device modules
+/-[20+(18*N*
Z0)]
a
-30
30
ps
Propagation delay variation of RSL signals with respect to
T
PD
for 16 device modules
+/-[24+(18*N*
Z0)]
a
-50
50
ps
a. Where:
N = Number of RDRAM devices installed on the RIMM module
Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)
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