參數(shù)資料
型號: MR0S16AVTS35C
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM
中文描述: 256K x 16位的3.3V異步磁阻隨機存取內存
文件頁數(shù): 14/22頁
文件大小: 154K
代理商: MR0S16AVTS35C
MR2A16A Data Sheet, Rev. 4
14
Freescale Semiconductor
Timing Specifications
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
1, 2, 3, 4, 5, 6
Parameter
Symbol
t
AVAV
t
AVBL
t
AVBH
t
AVBH
t
BLEH
t
BLWH
t
BLEH
t
BLWH
t
DVBH
t
BHDX
t
BHAX
Min
35
0
18
20
Max
Unit
ns
ns
ns
ns
Write cycle time
7
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Byte pulse width (G high)
15
ns
Byte pulse width (G low)
15
ns
Data valid to end of write
Data hold time
Write recovery time
10
0
12
ns
ns
ns
NOTES:
1
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
2
3
4
5
6
7
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