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| 型號(hào)： | MQ83C154TXXX-12P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 38/234頁(yè) |
| 文件大?。?/td> | 61013K |
| 代理商： | MQ83C154TXXX-12P883 |
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132
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
18.7.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM2[1:0] = 3) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A, and set at BOTTOM. In inverting
Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope oper-
ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that
uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectifi-
cation, and DAC applications. High frequency allows physically small sized external components (coils,
capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The
TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2A and TCNT2.
Figure 18-6. Fast PWM Mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the
COM2A[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM2A[1:0] to three (See Table 18-4 on page 139). The actual OC2A value will only be visible on the port pin
if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the
OC2A Register at the compare match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at
the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM2A[1:0] bits.)
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2
3
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4
5
6
7
f
OCnxPWM
fclk_I/O
N 256
------------------
=
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