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參數(shù)資料
| 型號： | MPC992FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 375 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大小： | 89K |
| 代理商： | MPC992FA |
MPC992
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
269
Figure 3. Power Supply Filter
VCCA
VCC
MPC992
0.01F
22F
0.01F
3.3V
RS=10-15
A higher level of attenuation can be achieved by replacing the
resistor with an appropriate valued inductor. A 1000
H choke
will show a significant impedance at 10KHz frequencies and
above. Because of the current draw and the voltage that must
be maintained on the VCCA pin a low DC resistance inductor
is required (less than 15
). Generally the resistor/capacitor
filter will be cheaper, easier to implement and provide an
adequate level of supply filtering.
The MPC992 provides sub–nanosecond output edge rates
and thus a good power supply bypassing scheme is a must. The
important aspect of the layout for the MPC992 is low impedance
connections between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors with
good PCB layout techniques will produce effective capacitor
resonances at frequencies adequate to supply the instanta-
neous switching current for the MPC992 outputs. It is imperative
that low inductance chip capacitors are used; it is equally
important that the board layout does not introduce back all of the
inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power plane
should be avoided and multiple large vias should be used to tie
the capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance and
thus maximize the series resonant point of the bypass
capacitors.
No active signal lines should pass below the crystal interface
to the MPC992. The oscillator is a series resonant circuit and
the voltage amplitude across the crystal is relatively small. It is
imperative that no actively switching signals cross under the
crystal as crosstalk energy coupled to these lines could
significantly impact the jitter of the device. Special attention
should be paid to the layout of the crystal to ensure a stable, jitter
free interface between the crystal and the on–board oscillator.
In addition, the crystal interface circuitry will be adversely
affected by activity on the PECL_CLK inputs. Therefore, it is
recommended that the PECL input signals be static when the
crystal oscillator circuitry is being used.
Although the MPC992 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter and
bypass schemes discussed in this section should be adequate
to eliminate power supply noise related problems in most
designs.
2
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