- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2014 > MPC96877VK (IDT, Integrated Device Technology Inc)IC CLK DRIVER 1:10 SDRAM 52-BGA PDF資料下載
參數(shù)資料
| 型號： | MPC96877VK |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 0K |
| 描述： | IC CLK DRIVER 1:10 SDRAM 52-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標準包裝： | 1 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR2，SDRAM |
| 輸入： | 時鐘 |
| 輸出： | SSTL-18 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-BGA |
| 包裝： | 托盤 |
MPC96877
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
551
Table 3. Absolute Maximum Ratings Over Free-Air Operating Range1
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Parameter
Value
Supply voltage range, VDDQ or AVDD
–0.5 V to 2.5 V
Input voltage range, VI2, 3
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5 V maximum.
–0.5 V to VDDQ + 0.5 V
Output voltage range, VO1, 2
–0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ)
±50 mA
Output clamp voltage, IOK (VO < 0 or VO > VDDQ)
±50 mA
Continuous output current, IO (VO = 0 to VDDQ)
±50 mA
Continuous current through each VDDQ or GND
±100 mA
Storage temperature range, TSTG
–65
°C to 150°C
Table 4. Recommended Operating Conditions
Rating
Parameter
Affected Pins
Min
Nom
Max
Unit
Output supply voltage
VDDQ
1.7
1.8
1.9
V
Supply voltage1
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and not timing parameters are guaranteed.
AVDD
VDDQ
Low-level input voltage2
2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12. Time Delay between OE and Clock
Output for definition. For CK and CK the VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
VIL
OE, OS, CK, CK
0.35 x VDDQ
V
High-level input voltage2
VIH
OE, OS, CK, CK
0.65 x VDDQ
High-level output current
IOH
–9
mA
Low-level output current
IOL
9
mA
Input differential-pair cross voltage
VIX
(VDDQ/2) –0.15
(VDDQ/2) +0.15
V
Input voltage level
VIN
–0.3
VDDQ +0.3
Input differential-pair voltage2
(see Figure 9. Half-Period Jitter)
VID
DC
0.3
VDDQ +0.4
AC
0.6
VDDQ +0.4
Operating free-air temperature
0
70
°C
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
NETCOM
IDT 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9773AE | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| MPC9850VF | IC PLL CLOCK GENERATOR 100MAPBGA |
| MPC9855VM | IC PLL CLOCK GENERATOR 100MAPBGA |
| MPC9893AE | IC PLL CLK GEN 1:12 3.3V 48-LQFP |
| MSTM-S3-TR-19.44M | IC MOD TIMING 19.440MHZ STRAT 3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC96877VKR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC970 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
| MPC972FA | 制造商:Freescale Semiconductor 功能描述: |
| MPC972H10 F44A WAF | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。