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參數資料
| 型號： | MPC9352AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 標準包裝： | 250 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:11 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9352 REVISION 8 JANUARY 31, 2013
11
2013 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Due to the statistical nature of I/O jitter, a RMS value (1
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 11.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation,
an I/O jitter confidence factor of 99.7% (
3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –445 ps to 395 ps relative to CCLK:
tSK(PP) = [–200ps...150ps] + [-200ps...200ps] +
[(15ps
–3)...(15ps 3)] + tPD, LINE(FB)
tSK(PP) = [–445ps...395ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 9
can be used for a more precise timing performance analysis.
Figure 9. Max. I/O Jitter versus Frequency
Driving Transmission Lines
The MPC9352 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to application note AN1091. In
most high performance clock networks, point-to-point
distribution of signals is the method of choice. In a
point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9352 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 10
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme, the fanout of the MPC9352 clock driver is
effectively doubled due to its capability to drive multiple lines.
Figure 10. Single versus Dual Transmission Lines
The waveform plots in Figure 11 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9352 output buffer
is more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9352. The output waveform
in Figure 11 shows a step in the waveform. This step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36
series resistor,
plus the output impedance, does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL =VS (Z0 (RS+R0 +Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18+17+25))
=1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Table 11. Confidence Factor CF
CF
Probability of clock edge within the distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
30
25
20
15
10
5
0
200
225
250
275
300
325
VCO frequency [MHz]
t JI
T(
)[ps
]m
s
Max. I/O Jitter versus frequency
350
375
400
14
IN
MPC9352
Output
Buffer
RS = 36
ZO = 50
OutA
14
IN
MPC9352
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
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| MPC9352FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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