參數(shù)資料
型號: MPC9350D
廠商: Motorola, Inc.
英文描述: LOW VOLTAGE PLL CLOCK DRIVER
中文描述: 低壓PLL時鐘驅(qū)動器
文件頁數(shù): 9/12頁
文件大?。?/td> 282K
代理商: MPC9350D
MPC9350
TIMING SOLUTIONS
MOTOROLA
Figure 7. TCLK MPC9350 AC test reference for Vcc = 3.3V and Vcc = 2.5V
Figure 8. Output–to–output Skew tSK(O)
PULSE
GENERATOR
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9350 DUT
VTT
VTT
Figure 9. Output Duty Cycle (DC)
Figure 10. Transition Time Test Reference
Figure 11. Cycle–to–cycle Jitter
Figure 12. Period Jitter
The pin–to–pin skew is defined as the worst case difference in propagation
delay between any simlar delay path within a single device
The time fromthe PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
The time fromthe maximumlow level voltage to mnimumhigh level of a
clock signal, expressed in ns
The variation in cycle time of a signal between adjacent cycles, over a
randomsample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a randomsample of cycles
VCC
VCC
GND
2
VCC
VCC
2
GND
VCC
VCC
GND
2
tSK(O)
tP
T0
DC = tP/T0
x
100%
tF
tR
TN
TJIT(CC) =
|
TN–TN+1
|
TN+1
TJIT(P) =
|
TN–1
/
f0
|
T0
VCC=3.3V
2.4
VCC=2.5V
1.8V
0.55
0.6V
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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參數(shù)描述
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