參數(shù)資料
型號(hào): MPC9330
廠商: Motorola, Inc.
英文描述: 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
中文描述: 3.3 / 2.5V的1:6的LVCMOS PLL時(shí)鐘發(fā)生器
文件頁數(shù): 6/16頁
文件大?。?/td> 225K
代理商: MPC9330
MPC9330
MOTOROLA
TIMING SOLUTIONS
6
Table 8: DC CHARACTERISTICS
(VCC = 2.5V
±
5%, TA = –40
°
C to 85
°
C)
Symbol
Characteristics
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
Input Current
ICC_PLL
Maximum PLL Supply Current
ICC
Maximum Quiescent Supply Current
a.
The MPC9330 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission line
to a termination voltage of VTT. Alternatively, the device drives up to two 50
series terminated transmission lines per output.
Table 9: AC CHARACTERISTICS
(VCC = 2.5V
±
5%, TA = –40
°
C to 85
°
C)a b
Symbol
Characteristics
fref
PLL mode, external feedback
÷
8 feedback
÷
12 feedback
÷
16 feedback
÷
24 feedback
PLL mode, internal feedback
÷
16 feedback)
Input Reference Frequency in PLL bypass modee
fVCO
fXTAL
fMAX
Output Frequency
÷
8 output
÷
12 output
÷
16 output
÷
24 output
frefDC
Reference Input Duty Cycle
tr, tf
CCLK Input Rise/Fall Time
t(
)
Propagation Delay
CCLK or PCLK to FB_IN
(static phase offset)
Output-to-Output Skewh
DC
Output Duty Cycle
tr, tf
Output Rise/Fall Time
tPLZ, HZ
Output Disable Time
tPZL, LZ
Output Enable Time
tJIT(CC)
Cycle-to-cycle jitter
tJIT(PER)
Period Jitter
RMS (1 )
tJIT(
)
I/O Phase Jitter
RMS (1 )
BW
PLL closed loop bandwidthj
÷
4 feedback
÷
8 feedback
÷
12 feedback
÷
16 feedback
÷
24 feedback
tLOCK
Maximum PLL Lock Time
a.
All AC characteristics are design targets and subject to change upon device characterization.
b.
AC characteristics apply for parallel output termination of 50
to VTT.
c.
PLL mode requires PLL_EN = 0 to enable the PLL.
d.
÷
4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one
÷
2 output to FB_IN.
See Table 1 to Table 3 for other feedback configurations.
e.
In bypass mode, the MPC9330 divides the input reference clock.
f.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO
÷
FB.
g.
The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
h.
See application section for part–to–part skew calculation.
i.
See application section for a jitter calculation for other confidence factors than 1 .
j.
–3 dB point of PLL transfer characteristics.
Min
1.7
–0.3
1.8
Typ
Max
Unit
V
V
V
V
Condition
LVCMOS
LVCMOS
IOH=-15 mAa
IOL= 15 mA
VCC + 0.3
0.7
0.6
17 - 20
±
200
5.0
1.0
μ
A
mA
mA
VIN = VCC or GND
VCCA Pin
All VCC Pins
2.0
Min
50
25
16.67
12.5
8.33
12.5
Typ
Max
100
50
33.3
25
16.67
25
TBD
400
20
100
50
33.3
25
16.67
60
1.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Condition
PLL locked
Input Reference Frequencyc
÷
4 feedbackd
VCO Lock Frequency Rangef
Crystal Interface Frequency Rangeg
200
10
50
25
16.67
12.5
8.33
40
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ps
÷
4 outputg
PLL locked
0.7 to 1.7V
FB_SEL=1 &
PLL locked
±
100
tsk(o)
150
55
1.0
10
10
ps
%
ns
ns
ns
ps
ps
ps
kHz
kHz
kHz
kHz
kHz
ms
45
0.1
50
0.6 to 1.8V
RMS (1 )i
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
10
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