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參數(shù)資料
| 型號(hào)： | MPC9239FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | MPC9239FN |
4
MPC9239
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
419
Table 1. Pin Configuration
Pin
I/O
Default
Type
Function
XTAL_IN,
XTAL_OUT
Analog
Crystal oscillator interface
FREF_EXT
Input
0
LVCMOS
Alternative PLL reference input
FOUT, FOUT
Output
LVPECL
Differential clock output
TEST
Output
LVCMOS
Test and device diagnosis output
XTAL_SEL
Input
1
LVCMOS
PLL reference select input
PWR_DOWN
Input
0
LVCMOS
Configuration input for power down mode. Assertion (deassertion) of power down will
decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps.
PWR_DOWN assertion (deassertion) is synchronous to the input reference clock.
S_LOAD
Input
0
LVCMOS
Serial configuration control input. This inputs controls the loading of the configuration
latches with the contents of the shift register. The latches will be transparent when this
signal is high, thus the data must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS
Parallel configuration control input. this input controls the loading of the configuration
latches with the content of the parallel inputs (M and N). The latches will be transparent
when this signal is low, thus the parallel data must be stable on the low-to-high transition
of P_LOAD. P_LOAD is state sensitive.
S_DATA
Input
0
LVCMOS
Serial configuration data input.
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input.
M[0:6]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of runt
pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L,
FOUT = H).
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
NC
Do not connect
Table 2. Output frequency range and PLL Post-divider N
PWR_DOWN
N
VCO Output
f
diii
FOUT frequency range
1
0
frequency division
0
2
200 - 450 MHz
0
1
4
100 - 225 MHz
0
1
0
8
50 - 112.5 MHz
0
1
400 - 900 MHz
1
0
32
12.5 - 28.125 MHz
1
0
1
64
6.25 - 14.0625 MHz
1
0
128
3.125 - 7.03125 MHz
1
16
25 - 56.25 MHz
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