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參數(shù)資料
| 型號： | MPC880CVR66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/87頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC 66MHZ 357PBGA |
| 標準包裝： | 44 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
16
Freescale Semiconductor
Layout Practices
Figure 5. Example Voltage Sequencing Circuit
9
Layout Practices
Each VDD pin on the MPC885/MPC880 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground
using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package.
Each board designed should be characterized and additional appropriate decoupling capacitors should be
used if required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and
GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board
employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC885/MPC880 have fast rise and fall times. Printed-circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For
more information, please refer to the MPC885 PowerQUICC Family Reference Manual, Section 14.4.3,
“Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).”
10 Bus Signal Timing
The maximum bus speed supported by the MPC885/MPC880 is 80 MHz. Higher-speed parts must be
operated in half-speed bus mode (for example, an MPC885/MPC880 used at 133 MHz must be configured
for a 66 MHz bus). Table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and
Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode.
VDDH
VDDL
1N5820
MUR420
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| MPC880CZP133 | 功能描述:微處理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC880CZP66 | 功能描述:微處理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC880VR133 | 功能描述:微處理器 - MPU 133 MHz 176 MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC880VR133 | 制造商:Freescale Semiconductor 功能描述:IC 32BIT MPU 133MHZ BGA-357 |
| MPC880VR66 | 功能描述:微處理器 - MPU 66 MHz 87 MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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