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    參數(shù)資料
    型號: MPC8572ECVTAULD
    廠商: Freescale Semiconductor
    文件頁數(shù): 124/138頁
    文件大小: 0K
    描述: MPU POWERQUICC III 1023-PBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 1.333GHz
    電壓: 1.1V
    安裝類型: 表面貼裝
    封裝/外殼: 1023-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
    包裝: 托盤
    MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    86
    Freescale Semiconductor
    PCI Express
    16.4.3
    Differential Receiver (RX) Input Specifications
    Table 63 defines the specifications for the differential input at all receivers (RXs). The parameters are
    specified at the component pins.
    Table 63. Differential Receiver (RX) Input Specifications
    Symbol
    Parameter
    Min
    Nominal
    Max
    Units
    Comments
    UI
    Unit Interval
    399.88
    400
    400.12
    ps
    Each UI is 400 ps ± 300 ppm. UI does not
    account for Spread Spectrum Clock
    dictated variations. See Note 1.
    VRX-DIFFp-p
    Differential Input
    Peak-to-Peak
    Voltage
    0.175
    1.200
    V
    VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|
    See Note 2.
    TRX-EYE
    Minimum
    Receiver Eye
    Width
    0.4
    UI
    The maximum interconnect media and
    Transmitter jitter that can be tolerated by the
    Receiver can be derived as TRX-MAX-JITTER
    = 1 - TRX-EYE= 0.6 UI.
    See Notes 2 and 3.
    TRX-EYE-MEDIAN-to-MAX
    -JITTER
    Maximum time
    between the jitter
    median and
    maximum
    deviation from
    the median.
    0.3
    UI
    Jitter is defined as the measurement
    variation of the crossing points (VRX-DIFFp-p
    = 0 V) in relation to a recovered TX UI. A
    recovered TX UI is calculated over 3500
    consecutive unit intervals of sample data.
    Jitter is measured using all edges of the
    250 consecutive UI in the center of the 3500
    UI used for calculating the TX UI. See
    Notes 2, 3 and 7.
    VRX-CM-ACp
    AC Peak
    Common Mode
    Input Voltage
    ——
    150
    mV
    VRX-CM-ACp = |VRXD+ +VRXD-|/2 -
    VRX-CM-DC
    VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2
    See Note 2
    RLRX-DIFF
    Differential
    Return Loss
    15
    dB
    Measured over 50 MHz to 1.25 GHz with
    the D+ and D- lines biased at +300 mV and
    -300 mV, respectively.
    See Note 4
    RLRX-CM
    Common Mode
    Return Loss
    6
    dB
    Measured over 50 MHz to 1.25 GHz with
    the D+ and D- lines biased at 0 V. See Note
    4
    ZRX-DIFF-DC
    DC Differential
    Input Impedance
    80
    100
    120
    Ω
    RX DC Differential mode impedance. See
    Note 5
    ZRX-DC
    DC Input
    Impedance
    40
    50
    60
    Ω
    Required RX D+ as well as D- DC
    Impedance (50 ± 20% tolerance). See
    Notes 2 and 5.
    ZRX-HIGH-IMP-DC
    Powered Down
    DC Input
    Impedance
    200 k
    Ω
    Required RX D+ as well as D- DC
    Impedance when the Receiver terminations
    do not have power. See Note 6.
    VRX-IDLE-DET-DIFFp-p
    Electrical Idle
    Detect Threshold
    65
    175
    mV
    VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-|
    Measured at the package pins of the
    Receiver
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