參數(shù)資料
型號： MPC8572CVTAVNE
廠商： Freescale Semiconductor
文件頁數(shù)： 81/138頁
文件大小： 0K
描述： MPU POWERQUICC III 1023FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
47
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.3.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver
characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver
inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 25, respectively.
8.3.4.1
SGMII Transmit AC Timing Specifications
Table 40 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
8.3.4.2
SGMII Receive AC Timing Specifications
Table 41 provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported. Clock is recovered from the data. Figure 24 shows the SGMII receiver input compliance mask
eye diagram.
Table 40. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—
0.35
UI p-p
—
Unit Interval
UI
799.92
800
800.08
ps
1
VOD fall time (80%-20%)
tfall
50
—
120
ps
—
VOD rise time (20%-80%)
trise
50
—
120
ps
—
Notes:
1. Each UI is 800 ps ± 100 ppm.
Table 41. SGMII Receive AC Timing Specifications
At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
1
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
—
UI p-p
1
Sinusoidal Jitter Tolerance
JSIN
0.1
—
UI p-p
1
Total Jitter Tolerance
JT
0.65
—
UI p-p
1
Bit Error Ratio
BER
—
10-12
——
Unit Interval
UI
799.92
800
800.08
ps
2
AC Coupling Capacitor
CTX
5
—
200
nF
3
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
4. See
RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.
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