參數(shù)資料
型號(hào)： MPC8568VTAUJJ
廠商： Freescale Semiconductor
文件頁數(shù)： 13/139頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
11
Electrical Characteristics
2.1.2
Recommended Operating Conditions
Table 3 provides the recommended operating conditions for this device. Note that the values in Table 3 are
the recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
Input voltage
DDR/DDR2 DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
DDR/DDR2 DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V4, 5
Local bus signals
BVIN
–0.3 to (BVDD + 0.3)
—
DUART, SYSCLK, system control and power
management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
Storage temperature range
TSTG
–55 to 150
C
C—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 2.
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit Notes
Core supply voltage
VDD
1.1 V ± 55 mV
V
—
PLL supply voltage
AVDD_PLAT,
AVDD_CORE,
AVDD_CE,
AVDD_PCI,
AVDD_LBIU,
AVDD_SRDS
1.1 V ± 55 mV
V
—
Core power supply for SerDes transceiver
SCOREVDD
1.1 V ± 55 mV
V
—
Pad power supply for SerDes transceiver
XVDD
1.1 V ± 55 mV
V
—
DDR and DDR2 DRAM I/O voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol
Max Value
Unit Notes
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