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參數(shù)資料
| 型號： | MPC855TCVR66D4 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 66MHZ 357-PBGA |
| 標準包裝： | 44 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
MOTOROLA
MPC855T Communications Controller Technical Summary
9
MPC855T Architecture Overview
Independent transmit and receive buffer descriptor rings located in external memory allow nearly unlimited
exibility in memory management of transmit and receive data frames. Locating buffer descriptors in
external memory has two advantages—rst, external memory (i.e., DRAM) is low cost; secondly, descriptor
rings in external memory have no inherent size limitations, allowing the memory management to be
optimized according to specic system needs.
1.2.3
System Interface Unit (SIU)
The SIU on the MPC855T integrates general-purpose features useful in almost any 32-bit processor system,
enhancing the performance provided by the system integration module (SIM) on the MC68360 QUICC
device.
Although the embedded MPC8xx core is always a 32-bit device internally, it may be congured to operate
with an 8-, 16- or 32-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is
supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus
mode.
The SIU also provides power management functions, reset control, decrementer, time base and real-time
clock.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,
SDRAM, EPROM, Flash EPROM, SRDRAM, EDO and other peripherals with two-clock access. The
memory controller supports bursting and variable memory block sizes from 32 Kbytes to 256 Mbytes. The
memory controller provides 0–15 wait states for each bank of memory and can use address type matching
to qualify each memory bank access. It also provides four byte-enable signals for varying width devices,
one output enable signal, and one boot chip select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks are dened in depths of 256
and 512 Kbytes, and 1, 2, 4, 8, 16, 32, and 64 Mbytes for all port sizes. In addition, memory depth is dened
as 64 Kbytes and 128 Kbytes for 8-bit memory or 128 Mbytes and 256 Mbytes for 32-bit memory. The
DRAM controller supports page mode access for successive transfers within bursts. The MPC855T supports
a glueless interface to one bank of DRAM; external buffers are required for additional memory banks. The
refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset,
disable refresh modes, and stacking up to seven refresh cycles. The DRAM interface uses a programmable
state machine to support almost any memory interface.PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface
supports up to two independent PCMCIA sockets requiring only external transceivers/buffers. The interface
provides eight memory or I/O windows where each window is allocated to a particular socket. If only one
PCMCIA port is being used, the unused PCMCIA port may be used as general-purpose input with interrupt
capability.
1.2.4
Communications Processor Module (CPM)
The MPC855T, like the earlier generation MPC850/860 family, implements a dual- processor architecture.
This dual-processor architecture provides both a high-performance, general-purpose processor for
application programming use as well as a special-purpose communications processor module (CPM)
uniquely designed for communications needs.
The CPM contains features that allow the 855T to excel in communications and networking products. These
features may be divided into three subgroups:
Communications processor (CP)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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