參數(shù)資料
型號(hào): MPC8555EPXAKE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 2/88頁(yè)
文件大小: 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 600MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
10
Freescale Semiconductor
Electrical Characteristics
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach ten percent of theirs.
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay does not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the VDD
core supply, the I/Os on the MPC8555E may drive a logic one or zero during
power-up.
2.1.3
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8555E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value
Unit
Core supply voltage
VDD
1.2 V ± 60 mV
1.3 V± 50 mV (for 1 GHz only)
V
PLL supply voltage
AVDD
1.2 V ± 60 mV
1.3 V ± 50 mV (for 1 GHz only)
V
DDR DRAM I/O voltage
GVDD
2.5 V ± 125 mV
V
Three-speed Ethernet I/O voltage
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V
PCI, local bus, DUART, system control and power management,
I2C, and JTAG I/O voltage
OVDD
3.3 V ± 165 mV
V
Input voltage
DDR DRAM signals
MVIN
GND to GVDD
V
DDR DRAM reference
MVREF
GND to GVDD
V
Three-speed Ethernet signals
LVIN
GND to LVDD
V
PCI, local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN
GND to OVDD
V
Die-junction Temperature
Tj
0 to 105
°C
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