參數(shù)資料
型號: MPC8548EVTAVHB
廠商: Freescale Semiconductor
文件頁數(shù): 78/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
32
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC)
Figure 10 shows the GMII receive AC timing diagram.
Figure 10. GMII Receive AC Timing Diagram
8.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
Table 28. MII Transmit AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
2
—400
ns
TX_CLK clock period 100 Mbps
tMTX
—40—
ns
TX_CLK duty cycle
tMTXH/tMTX
35
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
1
5
15
ns
TX_CLK data clock rise (20%–80%)
tMTXR
2
1.0
4.0
ns
TX_CLK data clock fall (80%–20%)
tMTXF
2
1.0
4.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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