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參數(shù)資料
| 型號(hào)： | MPC8545EHXATG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 7/151頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC III 783-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.2GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
104
Freescale Semiconductor
Package Description
25.These are test signals for factory use only and must be pulled up (100
–1 k) to OV
DD for normal machine operation.
26.Independent supplies derived from board VDD.
27.Recommend a pull-up resistor (~1 k
) be placed on this pin to OV
DD.
29. The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], TSEC4_TXD3/TSEC3_TXD7,
HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
30.This pin requires an external 4.7-k
pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively
driven.
31.This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control.
32.These pins must be connected to XVDD.
33.TSEC2_TXD1, TSEC2_TX_ER are multiplexed as cfg_dram_type[0:1]. They must be valid at power-up, even before
HRESET assertion.
34.These pins must be pulled to ground through a 300-
(±10%) resistor.
35.When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as ‘no
connect’ or terminated through 2–10 k
pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not
connected to any other PCI device. The PCI block drives the PCIn_AD pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
36.MDIC0 is grounded through an 18.2-
precision 1% resistor and MDIC1 is connected to GV
DD through an 18.2- precision
1% resistor. These pins are used for automatic calibration of the DDR IOs.
38.These pins must be left floating.
39. If PCI1 or PCI2 is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI1_CLK or PCI2_CLK.
Otherwise the processor will not boot up.
40.These pins must be connected to GND.
101.This pin requires an external 4.7-k
resistor to GND.
102.For Rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during
POR configuration are don’t care.
103.If these pins are not used as GPINn (general-purpose input), they must be pulled low (to GND) or high (to LVDD) through
2–10 k
resistors.
104.These must be pulled low to GND through 2–10 k
resistors if they are not used.
105.These must be pulled low or high to LVDD through 2–10 k resistors if they are not used.
106.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b10 during POR configuration; for rev. 1.x silicon, the pin values during POR
configuration are don’t care.
107.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b01 during POR configuration; for rev. 1.x silicon, the pin values during POR
configuration are don’t care.
108.For rev. 2.x silicon, DMA_DACK[0:1] must be 0b11 during POR configuration; for rev. 1.x silicon, the pin values during POR
configuration are don’t care.
109.This is a test signal for factory use only and must be pulled down (100
– 1 k) to GND for normal machine operation.
110.These pins must be pulled high to OVDD through 2–10 k resistors.
111.If these pins are not used as GPINn (general-purpose input), they must be pulled low (to GND) or high (to OVDD) through
2–10 k
resistors.
112.This pin must not be pulled down during POR configuration.
113.These should be pulled low or high to OVDD through 2–10 k resistors.
Table 71. MPC8548E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
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