參數(shù)資料
型號(hào): MPC8544VTALFA
廠商: Freescale Semiconductor
文件頁數(shù): 53/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 667MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
40
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.7.5
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.7.5.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 38.
Figure 23 shows the RMII transmit AC timing diagram.
Figure 23. RMII Transmit AC Timing Diagram
Table 38. RMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
REF_CLK clock period
tRMT
15.0
20.0
25.0
ns
REF_CLK duty cycle
tRMTH
35
50
65
%
REF_CLK peak-to-peak jitter
tRMTJ
——
250
ps
Rise time REF_CLK (20%–80%)
tRMTR
1.0
2.0
ns
Fall time REF_CLK (80%–20%)
tRMTF
1.0
2.0
ns
REF_CLK to RMII data TXD[1:0], TX_EN delay
tRMTDX
1.0
10.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
REF_CLK
TXD[1:0]
tRMTDX
tRMT
tRMTH
tRMTR
tRMTF
TX_EN
TX_ER
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