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| 型號： | MPC853TZT66A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC 66MHZ 256-PBGA |
| 標準包裝： | 60 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 66MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
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MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor
13
Layout Practices
10 Layout Practices
Each VDD pin on the MPC853T should be provided with a low-impedance path to the board’s supply. Each GND
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1-F bypass capacitors
located as close as possible to the four sides of the package. Each board designed should be characterized, and
additional appropriate decoupling capacitors should be used if required. Capacitor leads and associated printed
circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC853T have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads, as well as parasitic capacitances
caused by the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with
higher capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all
unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels
on the PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN,
VSSSYN, VSSSYN1)” in the MPC866 PowerQUICC Family User’s Manual.
11 Bus Signal Timing
The maximum bus speed supported by the MPC853T is 66 MHz. Table 7 shows the frequency ranges for standard
part frequencies in 1:1 bus mode.
Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode.
PCPAR
(Port C pin assignment register)
PCPAR[8:11]
PCDIR[14]
0
PCDIR
(Port C data direction register)
PCDIR[8:11]
PCDIR[14]
1
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency
50 MHz
66 MHz
Min
Max
Min
Max
Core Frequency
40
50
40
66.67
Bus Frequency
40
50
40
66.67
Table 6. Mandatory Reset Configuration of MPC853T (continued)
Register/Configuration
Field
Value
(binary)
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