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  • 參數(shù)資料
    型號: MPC8536CVTANG
    廠商: Freescale Semiconductor
    文件頁數(shù): 101/126頁
    文件大?。?/td> 0K
    描述: MPU PWRQUICC III 800MHZ 783PBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 800MHz
    電壓: 1V
    安裝類型: 表面貼裝
    封裝/外殼: 783-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
    包裝: 托盤
    MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    Electrical Characteristics
    Freescale Semiconductor
    76
    2.13.2
    eSDHC AC Timing Specifications
    This table provides the eSDHC AC timing specifications as defined in the following figure.
    Output low voltage
    VOL
    IOL = 100uA @OVDDmin
    0.125 * OVDD
    V
    Output high voltage
    VOH
    IOH = -100 uA
    OVDD - 0.2
    2
    Output low voltage
    VOL
    IOL = 2 mA
    0.3
    2
    Notes:
    1. The min VIL and VIH values are based on the respective min and max OVIN values found in Table 3.
    2. Open drain mode for MMC cards only.
    Table 56. eSDHC AC Timing Specifications
    At recommended operating conditions (see Table 3)
    Parameter
    Symbol1
    Min
    Max
    Unit
    Notes
    SD_CLK clock frequency:
    SD/SDIO Full speed/high speed mode
    MMC Full speed/high speed mode
    fSHSCK
    0
    25/50
    20/52
    MHz
    2, 5
    SD_CLK clock frequency - identification mode
    fSIDCK
    0
    100
    400
    KHz
    3, 5
    SD_CLK clock low time - High speed/Full speed mode
    tSHSCKL
    7/10
    ns
    5
    SD_CLK clock high time - High speed/Full speed mode
    tSHSCKH
    7/10
    ns
    5
    SD_CLK clock rise and fall times
    tSHSCKR/
    tSHSCKF
    —3
    ns
    5
    Input setup times: SD_CMD, SD_DATx, SD_CD to
    SD_CLK
    tSHSIVKH
    2.5
    ns
    4,5,6
    Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
    tSHSIXKH
    2.5
    ns
    5,6
    Output delay time: SD_CLK to SD_CMD, SD_DATx valid
    tSHSKHOV
    –3
    3
    ns
    5,6
    Notes:
    1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
    for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
    high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
    the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters
    representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:
    R (rise) or F (fall).
    2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed
    mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52MHz for a MMC card.
    3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required.
    4. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should
    not exceed 1 ns.
    5. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST+CCARD ≤ 40 pF
    6. The parameter values apply to both full speed and high speed modes.
    Table 55. eSDHC interface DC Electrical Characteristics (continued)
    At recommended operating conditions (see Table 3)
    Characteristic
    Symbol
    Condition
    Min
    Max
    Unit
    Notes
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