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| 型號： | MPC8379VRANG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 86/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 689-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 800MHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 689-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 689-TEPBGA II（31x31） |
| 包裝： | 托盤 |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
70
Freescale Semiconductor
Figure 48. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mVp-p.
20.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sections describe the SerDes reference clock requirements and some application
information.
20.2.1
SerDes Reference Clock Receiver Characteristics
Figure 49 shows a receiver reference diagram of the SerDes reference clocks.
SerDes Reference Clock Receiver Reference Circuit Structure
—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 49. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50
Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD
n_TX or
SD
n_RX
SD
n_TX or
SD
n_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2
× VDIFFp (not shown)
Vcm = (A + B)/2
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