參數(shù)資料
型號： MPC8379VRALGA
廠商： Freescale Semiconductor
文件頁數(shù)： 25/117頁
文件大小： 0K
描述： MPU POWERQUICC II 667MHZ 689PBGA
標準包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 667MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應商設備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
15
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the chip.
5.1
RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the device.
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the device.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
——
± 30
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
—
tPCI_SYNC_IN
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32
—
tCLKIN
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
—
tPCI_SYNC_IN
HRESET assertion (output)
512
—
tPCI_SYNC_IN
HRESET negation to negation (output)
16
—
tPCI_SYNC_IN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4—
tCLKIN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—
tPCI_SYNC_IN
Input hold time for POR config signals with respect to negation of HRESET
0—
ns
—
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