參數(shù)資料
型號： MPC8379ECVRALGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 73/114頁
文件大小： 1337K
代理商： MPC8379ECVRALGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
61
Serial ATA (SATA)
Table 54 provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
15.3
Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
15.3.1
Gen1i/1.5G Receiver Specifications
Table 55 provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 54. Gen 2i/3G Transmitter AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Channel speed
tCH_SPEED
—3.0
—
Gbps
—
Unit interval
TUI
333.2
333.33
335.11
ps
—
Total jitter
fC3dB=fBAUD/10
USATA_TXTJfB/10
——
0.3
UIp-p
1
Total jitter
fC3dB =fBAUD/500
USATA_TXTJfB/500
—
0.37
UIp-p
1
Total jitter
fC3dB =fBAUD/1667
USATA_TXTJfB/1667
—
0.55
UIp-p
1
Deterministic jitter
fC3dB =fBAUD/10
USATA_TXDJfB/10
—
0.17
UIp-p
1
Deterministic jitter
fC3dB =fBAUD/500
USATA_TXDJfB/500
—
0.19
UIp-p
1
Deterministic jitter
fC3dB =fBAUD/1667
USATA_TXDJfB/1667
—
0.35
UIp-p
1
Note:
1 Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 55. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
VSATA_RXDIFF
240
500
600
mVp-p
1
Differential Rx input impedance
ZSATA_RXSEIM
85
100
115
Ω
—
Note:
1 Voltage relative to common of either signal comprising a differential pair.
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