參數(shù)資料
型號(hào)： MPC8378VRANGA
廠商： Freescale Semiconductor
文件頁數(shù)： 63/128頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II 800MHZ 689PBGA
標(biāo)準(zhǔn)包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 800MHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
4
Freescale Semiconductor
1.3
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI/SGMII
Two controllers conform to IEEE Std 802.3, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588 standards
Support for Wake-on-Magic Packet, a method to bring the device from standby to full operating
mode
MII management interface for external PHY control and status
1.4
Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
1.5
Power Management Controller (PMC)
The power management controller includes the following features:
Provides power management when the device is used in both host and agent modes
Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
Supports MPC8349E backward-compatibility mode
1.6
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
1.7
DMA Controller, Dual I2C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
Supports misaligned transfers
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