參數(shù)資料
型號： MPC8378ECVRAGD
廠商： Freescale Semiconductor
文件頁數(shù)： 14/128頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 689-PBGA
標準包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應商設備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
110
Freescale Semiconductor
This table provides the operating frequencies for the TePBGA II package under recommended operating
conditions (see Table 3).
22.1
System PLL Configuration
The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency
depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 71 shows the multiplication factor encodings
for the system PLL.
NOTE
If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system
PLL VCO frequency = (CSB frequency)
× (System PLL VCO Divider).
If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL
VCO frequency = 2
× (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
Table 70. Operating Frequencies for TePBGA II
Parameter1
Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
e300 core frequency (
core_clk)
333
800
Coherent system bus frequency (
csb_clk)
133
400
DDR2 memory bus frequency (MCK)1
250
400
DDR1 memory bus frequency (MCK) 2
167
333
Local bus frequency (LCLK
n)1
—
133
Local bus controller frequency (
lbc_clk)
—
400
PCI input frequency (CLKIN or PCI_CLK)
25
66
eTSEC frequency
133
400
Security encryption controller frequency
—
200
USB controller frequency
—
200
eSDHC controller frequency
—
200
PCI Express controller frequency
—
400
Notes:
1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting
csb_clk,
MCK, LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,
USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.
2. The DDR data rate is 2
× the DDR memory bus frequency.
3. The local bus frequency is , , or 1/8 of the
lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the
csb_clk frequency (depending on RCWLR[LBCM]).
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