參數(shù)資料
型號: MPC8378CVRALGA
廠商: Freescale Semiconductor
文件頁數(shù): 77/128頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II 667MHZ 689PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
52
Freescale Semiconductor
11.2.1
Full-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 31. Full Speed Output Path
11.2.1.1
Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
No clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL
Eqn. 1
With clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY
Eqn. 2
tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY tISU tSFSKHOV
Eqn. 3
This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL =20 ns:
tDATA_DELAY + 20 < 40 + tCLK_DELAY 5 4
tDATA_DELAY < 11 + tCLK_DELAY
11.2.1.2
Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY tIH
Eqn. 4
Input at the
MPC8378E pins
SD CLK at the
MPC8378E pin
Output valid time: tSFSKHOV
Output hold time: tSFSKHOX
tIH (5 ns)
tCLK_DELAY
SD CLK at
Driving
Edge
Sampling
edge
the card pin
tISU (5 ns)
tDATA_DELAY
tSFSCKL
tSFSCK (clock cycle)
Output from the
MPC8378E Pins
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