參數(shù)資料
型號: MPC8377EVRANG
廠商: Freescale Semiconductor
文件頁數(shù): 54/127頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
32
Freescale Semiconductor
8.3.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
LVDD1
3.135
3.465
V
Output high voltage
IOH = –1.0 mA
LVDD1 = Min
VOH
2.10
LVDD1 +0.3
V
Output low voltage
IOL = 1.0 mA
LVDD1 = Min
VOL
GND
0.50
V
Input high voltage
VIH
2.00
V
Input low voltage
VIL
—0.80
V
Input high current
LVDD1 = Max
VIN
1 = 2.1 V
IIH
—30
μA
Input low current
LVDD1 = Max
VIN = 0.5 V
IIL
–600
μA
Table 33. MII Management AC Timing Specifications
Parameter
Symbol1
Min
Typical
Max
Unit
Note
MDC frequency
fMDC
—2.5
MHz
MDC period
tMDC
80
400
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO valid
tMDKHDV
2
× (tplb_clk × 8)
ns
MDC to MDIO delay
tMDKHDX
10
2
× (tplb_clk × 8)
ns
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time (20%–80%)
tMDCR
——
10
ns
MDC fall time (80%–20%)
tMDCF
——
10
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed.
3. Guaranteed by design.
4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
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