參數(shù)資料
型號(hào): MPC8377E-RDBA
廠商: Freescale Semiconductor
文件頁數(shù): 104/127頁
文件大小: 0K
描述: BOARD REF DES MPC8377 REV 2.1
設(shè)計(jì)資源: MPC8379E-RDB Ref Design Guide
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8377E
所含物品: 板,CD
相關(guān)產(chǎn)品: MPC8378EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
MPC8378EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8378EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
MPC8378EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8379EVRANG-ND - MPU PWRQUICC II 800MHZ 689TEPBGA
MPC8379EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8379EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
MPC8379EVRAGD-ND - MPU PWRQUICC II 400MHZ 689TEPBGA
MPC8377EVRALG-ND - MPU PWRQUICC II 667MHZ 689TEPBGA
MPC8377EVRAJF-ND - MPU PWRQUICC II 533MHZ 689TEPBGA
更多...
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
78
Freescale Semiconductor
This figure shows the SPI timing in slave mode (external clock).
Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in master mode (internal clock).
Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram
21 High-Speed Serial Interfaces (HSSI)
This chip features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications. See Table 1 for the interfaces supported.
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
21.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 51 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
SPICLK (input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
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