參數(shù)資料
型號: MPC8377CVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 103/127頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
77
20.2
SPI AC Timing Specifications
This table provides the SPI input and output AC timing specifications.
This figure provides the AC test load for the SPI.
Figure 48. SPI AC Test Load
These figures represent the AC timing from Table 70. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Output low voltage
IOL = 8.0 mA
VOL
—0.5
V
Output low voltage
IOL = 3.2 mA
VOL
—0.4
V
Table 70. SPI AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOV
28
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
4—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.
Table 69. SPI DC Electrical Characteristics (continued)
Parameter
Condition
Symbol
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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