
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
29
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
This figure shows the MII transmit AC timing diagram.
Figure 12. MII Transmit AC Timing Diagram
Table 29. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—40—
ns
TX_CLK duty cycle
tMTXH/tMTX
35
—
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
tMTKHDV
1
—
5—
15
ns
TX_CLK data clock rise time, (20% to 80%)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall time, (80% to 20%)
tMTXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER