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| 型號(hào)： | MPC8347VRAGDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620 |
| 封裝： | 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620 |
| 文件頁(yè)數(shù)： | 18/120頁(yè) |
| 文件大小： | 1349K |
| 代理商： | MPC8347VRAGDA |
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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
114
Freescale Semiconductor
System Design Information
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.
21.7
Pull-Up Resistor Requirements
The MPC8347EA requires high resistance pull-up resistors (10 k
Ω is recommended) on open-drain pins,
including I2C pins, the Ethernet Management MDIO pin, and EPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 43. Take care to ensure that these pins are maintained at a valid deasserted state
under normal operating conditions because most have asynchronous behavior, and spurious assertion
yields unpredictable results.
Refer to the PCI 2.3 specification for all pull-ups required for PCI.
21.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE Std. 1149.1 specification, but it is provided on all processors that implement the PowerPC
architecture. The MPC8347EA requires TRST to be asserted during reset conditions to ensure that the
JTAG boundary logic does not interfere with normal chip operation. While the TAP controller may be
forced to the reset state using only the TCK and TMS signals, systems typically assert TRST during
power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor
(COP) function, simply tying TRST to PORESET is not practical.
The PowerPC COP function allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface
connects through the JTAG port of the processor, with some additional status monitoring signals. The COP
port requires the ability to assert TRST independently without causing PORESET. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 43 allows the COP to assert HRESET or TRST independently, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown in Figure 43 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. It requires no more effort than adding an
unpopulated footprint for a header when needed. The COP interface has a standard header for connection
to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg
header). There is no standardized way to number the header, shown in Figure 43, so emulator vendors use
different pin numbering schemes. Some headers are numbered top-to-bottom then left-to-right, others use
left-to-right then top-to-bottom, and still others number the pins counter clockwise from pin 1 (as with an
IC). Regardless of the numbering scheme, the signal placement recommended in Figure 43 is common to
all known emulators.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MPC8347VRAGDB | 功能描述:微處理器 - MPU 8347 PBGA NOPB W/O ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8347VVAGD | 功能描述:IC MPU PWRQUICC II PRO 672-TBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MPC8347VVAGDB | 功能描述:微處理器 - MPU 8349 TBGA NO-PB W/O ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8347VVAJD | 功能描述:IC MPU PWRQUICC II PRO 672-TBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MPC8347VVAJDB | 功能描述:微處理器 - MPU 8349 TBGA NO-PB W/O ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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