參數(shù)資料
型號: MPC8347ECZUAGDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 78/120頁
文件大?。?/td> 1349K
代理商: MPC8347ECZUAGDA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
60
Freescale Semiconductor
PCI
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8347EA.
13.1
PCI DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the PCI interface of the MPC8347EA.
13.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8347EA. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8347EA
is configured as a host or agent device. Table 44 provides the PCI AC timing specifications at 66 MHz.
Table 43. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
2
OVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.3
0.8
V
Input current
IIN
VIN
1= 0 V or V
IN = OVDD
—±5
μA
High-level output voltage
VOH
OVDD = min,
IOH = –100 μA
OVDD – 0.2
V
Low-level output voltage
VOL
OVDD = min,
IOL = 100 μA
—0.2
V
Notes:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1.
Table 44. PCI AC Timing Specifications at 66 MHz6
Parameter
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—6.0
ns
2
Output hold from Clock
tPCKHOX
1—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to Clock
tPCIVKH
3.0
ns
2, 4
Input hold from Clock
tPCIXKH
0—
ns
2, 4
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
6. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
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